The output of the register is N bits (in our example we will use a 4 bit register). It has an N-bit Parallel input, which allows us to load the register with a new value. The load_shift signal allows us to determine the operating mode: when it is at 0, a new value is loaded when a rising edge of the clock arrives.
In Parallel In Serial Out (PISO) shift registers, the data is loaded onto the register in parallel format while it is retrieved from it serially. Figure 1 shows a PISO shift register which has a control-line and combinational circuit (AND and ) in addition to the basic register components fed with clock and clear pins. Here control line is used to select the functionality of the shift register amongst shift or load at a given instant of time. This is because when the line is made low, A 2 of all the combinational circuits become active while A 1 gates become inactive.
Related pages Thus the bits of the input data word (Data in) appearing as inputs to the gates A 2 are passed on as the outputs of at each individual combinational circuit. This causes the individual bits of the Data in to be loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B 1 which gets directly stored into FF 1 at the first clock tick). This indicates that all the bits of the input data word are stored into the register components at the same clock tick.
Next, line is driven high to activate the gates A 1 of the combinational circuits which inturn disables the gates A 2. This causes output bit of each to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF n) i.e. Output bit of FF 1 (Q 1) appears as the output of 1 (O 1) connected to D 2; Q 2 = output of O 2 = D 3 and so on. At this stage, if the rising edge of the clock pulse appears, then Q 1 appears at Q 2, Q 2 appears at Q 3, and Q n-1 appears at Q n.
This is nothing but right-shift of the data stored within the register by one-bit. Similarly it is seen that for each of the further clock pulses applied, one bit exits the PISO shift register through the output pin of n th flip-flop (Data out = Q n of FF n), which is nothing but the serial output.
Thus one requires n clock cycles to obtain the entire n-bit input data word as a serial output of PISO shift register. The truth table of the PISO shift register emphasizing the loading and retrieval processes is shown by Table I, while the corresponding wave forms are shown by Figure 2. By slightly modifying the design of Figure 1, one can make the data bits within the register to shift from right to left, thus obtaining a left-shift PISO shift-register (Figure 3). However the basic working principle remains unaltered.